The present invention relates broadly to ana1og-to-dig1ta1 (A/D) converters, and specifically to a calibration system to remove system nonlinearities in digitally corrected subranging A/D converters.
In order to build faster data acquisition systems, it is necessary to use circuitry which does not employ feedback techniques which slow the circuit. A good example of non feedback data acquisition circuits are the new high speed sample and hold circuits sold by commercial hybrid houses today. The much greater speed of these parts is paid for by higher harmonic distortion. In systems where extremely high, spurious free, dynamic range is required, these harmonics are generally the limiting factor. The problem is therefore to build a data acquisition system which operates at the high conversion rates needed in modern communications and radar systems while simultaneously maximizing the spurious free, dynamic range.
Various techniques and systems have been utilized to increase the conversion speed in A/D converters, so that they can be effectively used in data acquisition systems. Analog-to-digital converters can usually be classified into groups. One group includes high speed parallel converters in which the several digital bits are formed more or less simultaneously. The high speed of operation is obtained here at significant expenditures. The converters of the second group operate by successive approximation; progressively synthesized analog equivalents of progressively formed digital signals are compared individually with the analog information signal. Unfortunately, in both groups, a tradeoff must be made between conversion speed and conversion precision in the design of conventional subranging A/D converters.
The task of improving the conversion speed while minimizing the loss of precision has been alleviated, to some degree, by the following U.S. Patents, which are incorporated herein by reference.
U.S. Pat. No. 3,891,984 issued to Kerwin et al on June 24, 1975;
U.S. Pat. No. 4,070,665 issued to Glennon et al on Jan. 24, 1978;
U.S. Pat. No. 4,340,882 issued to Maio et al on July 20, 1982; and
U.S. Pat. No. 4,393,371 issued to Morgan-Smith on July 12, 1983.
The Kerwin et al and Morgan-Smith references both disclose A/D conversion systems. The Kerwin et al A/D converter provides subranging and multiple level error correction with comparison circuits. The Morgan-Smith A/D converter contains the sample and hold circuits, mentioned above, to sample and store the analog signal so that the stored signal can be compared to the varying levels of the input signals.
The Glennon et al and Maio et al references both disclose digital-to-analog (D/A) converter (DAC) systems. The patent of Maio et al discloses a D/A conversion system with a memory for storing compensation data that is used to compensate the output of the D/A converter at an address corresponding to the digital input signal. Glennon et al show another digital-to-analog converter which uses a ROM programmed to generate a correction signal for the converter.
The application of digitally corrected subranging in A/D converters can be enhanced if the digital correction is used in the form of a software calibrated DAC to calibrate the subrange and remove the system nonlinearities. The present invention is intended to apply this concept.